1. Field of the Invention
The present invention relates to a process for manufacturing integrated circuits, particularly of intelligent power semiconductor devices.
2. Discussion of the Related Art
In manufacturing integrated circuits, the problem of obtaining chip regions which are electrically insulated from one another exists. For example, in power semiconductor devices provided with on-chip driving circuitry (also called intelligent power semiconductor devices), the power device must be electrically insulated from the driving circuitry.
The most common technique to achieve this electrical insulation is PN junction isolation. However, this technique gives rise to some problems, especially related to the introduction of parasitic components.
Considering for example a Vertical Intelligent Power semiconductor device (VIP), such as an NPN power bipolar transistor constituted by an N++ emitter region diffused into a P-type base region which is in turn diffused into an N-type epitaxial layer representing the collector of the transistor. The driving circuitry is obtained inside a P-type well which is diffused into the N-type epitaxial layer and connected to the lowest voltage among those utilized in the chip to keep the P-type well/N-type epitaxial layer junction reverse biased. Inside the P-type well, vertical NPN transistors and lateral PNP transistors are generally obtained. In this structure, a number of parasitic bipolar transistors are present, both NPN and PNP, having base, emitter and collector represented by the various P-type or N-type regions inside the P-type well, the P-type well itself and the N-type epitaxial layer. Another PNP parasitic transistor has emitter, base and collector respectively represented by the P-type base region of the power transistor, the N-type epitaxial layer and the P-type well. All such parasitic components limit VIP performances.